The invention relates to a system carrier for freely programmable blocks (gate arrays) that are connected to one another by means of buses.
In the development of complex integrated circuits (IC) first of all logic designs are created, which are based on a speech-based description in a programming language, the hardware description language (HDL) as it is known. For the purpose of functional verification of highly integrated microelectronic circuits, it is usual to use logic simulation in the development phase. As a supplement to the simulation, in recent years specific platforms for the logic emulation have been used. The circuit, which is present as a network list and is to be verified, was partitioned onto freely programmable logic blocks (FPGA) which are connected by means of specific programmable switching matrices. This technique is known as rapid prototyping. The developer is therefore made capable of testing the circuit on the platform in an early development phase of a logic design before said circuit is cast in silicon.
The drawback with this system is that, because of the switching matrix, considerable propagation time delays have to be tolerated, which makes the verification of the logic design more difficult or even impossible. Added to this is the fact that the programmable blocks are placed fixedly on the platform and are connected to one another via the switching matrix by likewise fixed connections.